GX4002 Datasheet, PDF (17/74 Pages) Gennum Corporation – Dynamic on-chip power management control

The following registers enable and configure the automatic rate detect feature:
Register Name
CH0PLL_REG5
CH0RDET_REG1
CH1RDET_REG1
Register
Address^d
14
67
72
Parameter Name
CH0PLLBYPASS
CH0PLLAUTOBYPASSEN
CH0RATEDETRESET
CH0RATEDETEN
CH1RATEDETRESET
CH1RATEDETEN
Bit
Position
Access
1:1
RW
2:2
RW
0:0
RW
1:1
RW
0:0
RW
1:1
RW
Reset Value^b
0
1
0
1
0
1
Valid
Range^d
Function
0-1
When HIGH, forces CDR into bypass mode.
0-1
When HIGH, enables automatic bypass
mode for the Ch0 CDR.
0-1
When HIGH, resets the Ch0 path rate
detector.
0-1
When HIGH, enables the Ch0 path
automatic rate detector.
0-1
When HIGH, resets the Ch1 path rate
detector.
0-1
When HIGH, enables the Ch1 path
automatic rate detector.
The device can be configured to manually bypass each of the Ch1 and Ch0 CDRs
through the CH0PLLBYPASS and CH1PLLBYPASS controls when the automatic bypass
is disabled.
3.2 Channel 0 Path (Ch0)
The channel 0 path is comprised of a trace equalizer, a multi-rate CDR and an output
driver.
Ch0 Disable
Input
EQ
CDR
DR
Output
Figure 3-1: Channel 0 Path
3.2.1 Ch0 Equalization
The channel 0 path input has an equalizer with 6dB gain at 7GHz. The equalizer can be
bypassed through the following register:
Register Name
CH0_REG3
Register
Address^d
33
Parameter Name
CH0EQBOOST
Bit
Position
Access
0:0
RW
Reset Value^b
1
Valid
Range^d
Function
0-1
When HIGH, applies a fixed CH0 EQ boost of
6dB. 0dB if LOW.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
17 of 74
Proprietary & Confidential