GX4002 Datasheet, PDF (15/74 Pages) Gennum Corporation – Dynamic on-chip power management control

3.1.1.2 Soft Rate Select
The CH1PLLRATESEL and CH0PLLRATESEL bits can be programmed to select a rate
profile using the host interface. Setting these parameters and their associated valid
parameters (CH1PLLRATESELVAL and CH0PLLRATESELVAL) override the on-chip
automatic rate detection circuitry. CH0PLLRATESEL is logically OR'd with the RS0 pin,
while CH1PLLRATESEL is logically OR'd with RS1, so RS0 and RS1 must be LOW or
hi-impedance for the PLLRATESEL bits to function properly.
Register Name
CH0PLL_REG5
CH1PLL_REG5
Register
Address^d
14
14
24
24
Parameter Name
CH0PLLRATESEL
CH0PLLRATESELVAL
CH1PLLRATESEL
CH1PLLRATESELVAL
Bit
Position
Access
3:3
RW
4:4
RW
3:3
RW
4:4
RW
Reset Value^b
1
1
1
1
Valid
Range^d
Function
0-1
Selects data rates:
0 = 1.25 - 8.5G, 1= 10.3G or 14.025G.
0-1
When HIGH, CH0PLLRATESEL or RS0 are
valid, otherwise they are ignored.
0-1
Selects data rates:
0 = 1.25 - 8.5G, 1= 10.3G or 14.025G.
0-1
When HIGH, CH1PLLRATESEL or RS1 are
valid, otherwise they are ignored.
The default setting is the high (10Gb/s or 14.025Gb/s) data-rate profile, with the on-chip
automatic rate detection circuitry overridden.
3.1.1.3 Automatic Rate Detection
In addition to the controls outlined in the preceding tables, the auto rate detection
circuitry has the following controls. To enable operation of the auto rate detection
function, CH0RATEDETEN (or CH1RATEDETEN) can be set HIGH.
Register Name
CH0RDET_REG1
CH0RDET_REG2
CH1RDET_REG1
CH1RDET_REG2
Register
Address^d
67
68
72
73
Parameter Name
CH0RATEDETRESET
CH0RATEDETEN
CH0RATEDETRATEPER
CH1RATEDETRESET
CH1RATEDETEN
CH1RATEDETRATEPER
Bit
Position
Access
0
RW
1
RW
3:0
RW
0
RW
1
RW
3:0
RW
Reset Value^b
0
1
1000
0
1
1000
Valid
Range^d
Function
0-1
0-1
0-15
0-1
0-1
0-15
When HIGH, the Ch0 path rate detector is
reset.
When HIGH, enables the rate detector.
Rate detector rate period (0.3µs to 13ms,
100µs default).
When HIGH, the Ch1 path rate detector is
reset.
When HIGH, enables the rate detector
Rate detector rate period (0.3µs to 13ms,
100µs default).
If CH1RATEDETEN (or CH0RATEDETEN) is LOW, the CH1PLLRATESELVAL (or
CH0PLLRATESELVAL) bit must be HIGH, otherwise the device will be in an undefined
state.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
15 of 74
Proprietary & Confidential