MB15F73UL Datasheet, PDF (9/18 Pages) Fujitsu Component Limited. – ASSP Dual Serial Input PLL Frequency Synthesizer

Dec. 2000
Edition 2.0
MB15F73UL
Programmable Counter
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CC L S F A A A A A A A N N N N N NN NN NN
N N D W C 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11
1 2 S ^IF/RF IF/RF
CN1, 2
: Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SWIF/RF
: Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)
FCIF/RF
: Phase control bit for the phase detector(IF : FCIF, RF : FCRF)
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 3]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
RRRRRRRRRRRRRR
14 13 12 11 10 9 8 7 6 5 4 3 2 1
3
00000000000011
4
00000000000100
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
11111111111111
Note: • Divide ratio less than 3 is prohibited.
Table.3 LD/fout output Selectable Bit Setting
LD/fout pin state LDS
T1
T2
0
0
0
LD output
0
1
0
0
1
1
frIF
1
0
0
fout
frRF
1
1
0
output
fpIF
1
0
1
fpRF
1
1
1
9