MB15F73UL Datasheet, PDF (10/18 Pages) Fujitsu Component Limited. – ASSP Dual Serial Input PLL Frequency Synthesizer

MB15F73UL
Dec. 2000
Edition 2.0
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
NNNNNNNNNNN
11 10 9 8 7 6 5 4 3 2 1
3
00000000011
4
00000000100
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
11111111111
Note: • Divide ratio less than 3 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(N)
AAAAAAA
7654321
0
0000000
1
0000001
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1111111
Note: • Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
SW = ”1”
Prescaler
divide ratio
IF-PLL
RF-PLL
8/9
64/65
SW = ”0”
16/17
128/129
Table. 7 Phase Comparator Phase Switching Data Setting
FCIF,RF = 1
FCIF,RF = 0
DoIF,RF
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO Output
Frequency
VCO polarity
1
2
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
FC bit should be set.
1
2
VCO Input Voltage
10