MB15F73UL Datasheet, PDF (8/18 Pages) Fujitsu Component Limited. – ASSP Dual Serial Input PLL Frequency Synthesizer

MB15F73UL
Dec. 2000
Edition 2.0
n FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(P x N) + A} x fOSC ÷ R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
P: Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A: Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127, condition;A < N)
fOSC: Reference oscillation frequency
R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
Table1. Control Bit
Control bit
CN1
CN2
0
0
1
0
0
1
1
1
Destination of serial data
The programmable reference counter for the IF-PLL.
The programmable reference counter for the RF-PLL.
The programmable counter and the swallow counter for the IF-PLL
The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C CTT _{RR RRR RRRR RR RRRCX X X X}
N N _{1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 S}
12
CN1, 2
: Control bit
[Table. 1]
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) [Table. 2]
T1, 2
: LD/fout output setting bit
[Table. 3]
CS
: Charge pump current select bit
[Table. 8]
X
: Dummy bits(Set "0" or "1")
NOTE: Data input with MSB first.
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