MB15F73UL Datasheet, PDF (14/18 Pages) Fujitsu Component Limited. – ASSP Dual Serial Input PLL Frequency Synthesizer

MB15F73UL
n PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
LD
(FC bit = 1)
DoIF/RF
Z
tWU
H
(FC bit = 0)
DoIF/RF
Z
tWL
L
Dec. 2000
Edition 2.0
LD Output Logic Table
IF–PLL section
Locking state / Power saving state
Locking state / Power saving state
Unlocking state
Unlocking state
RF–PLL section
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
Unlocking state
LD output
H
L
L
L
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 2/fosc: i.e. tWU > 156.3ns when foscin = 12.8 MHz
tWL < 4/fosc: i.e. tWL < 312.5ns when foscin = 12.8 MHz
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