MB15F73UL Datasheet, PDF (13/18 Pages) Fujitsu Component Limited. – ASSP Dual Serial Input PLL Frequency Synthesizer

Dec. 2000
Edition 2.0
MB15F73UL
n SERIAL DATA INPUT TIMING
1st data
Data
Clock
MSB
2nd data
Control bit Invalid data
LSB
LE
t7
Parameter
t1
t2
t3
t4
t1
t2
t3
t4
t5
t6
On the rising edge of the clock, one bit of data is transferred into the shift register.
Min. Typ. Max. Unit
Parameter Min. Typ. Max.
20
–
20
–
30
–
30
–
–
ns
–
ns
–
ns
–
ns
t5
100
–
–
t6
20
–
–
t7
100
–
–
Unit
ns
ns
ns
Note: LE should be "L" when the data is transferred into the shift register.
13