MB15F73UL Datasheet, PDF (3/18 Pages) Fujitsu Component Limited. – ASSP Dual Serial Input PLL Frequency Synthesizer

Dec. 2000
Edition 2.0
MB15F73UL
n PIN DESCRIPTIONS
Pin No.
TSSOP BCC
Pin
name
1
19
OSCIN
2
20
GND
3
1
finIF
4
2
XfinIF
5
3
GNDIF
6
4
VccIF
7
5
PSIF
8
6
VpIF
9
7
DoIF
10
8
LD/fout
11
9
DoRF
12
10
VpRF
13
11
PSRF
14
12
VccRF
15
13
GNDRF
16
14
XfinRF
17
15
finRF
18
16
LE
19
17
Data
20
18
Clock
I/O
Descriptions
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
- Ground for OSC input buffer and the shift registor circuit.
I
Prescaler input pin for the IF-PLL section.
Connection to an external VCO should be AC coupling.
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
- Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section(except for the
- charge pump circuit), the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
Power saving mode control for the IF-PLL section. This pin must be set
I at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode
- Power supply voltage input pin for the IF-PLL charge pump.
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Lock detect signal output(LD)/ phase comparator monitoring outut
O (fout). The output signal is selected by a LDS bit in a serial data.
LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
- Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control for the RF-PLL section. This pin must be
I set at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode
-
Power supply voltage input pin for the RF-PLL section(except for the
charge pump circuit).
- Ground for the RF-PLL section.
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
I
Prescaler input pin for the RF-PLL.
Connction to an external VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
I When LE is set "H", data in the shift register is transferred to the corre-
sponding latch according to the control bit in a serial data.
Serial data input (with the schmitt trigger circuit.)
I
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
I One bit data is shifted into the shift register on a rising edge of the
clock.
3