MB91301A Datasheet, PDF (578/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

APPENDIX
Table C-3 Pin States in External Bus 8-Bit Mode
At initialization
Pin no.
Port
name
Function
(INIT)
Specified
function
name
name
Function
name
Initial
Bus width Bus width ^value
8 bit
8 bit
Sleep
mode
Stop mode
Bus released
(BGRNT)
HIZ=0
HIZ=1
CS CS not
shared shared
90
PJ0
SIN0
PJ0
PJ0
91
PJ1
SOT0
PJ1
PJ1
92
PJ2
SCK0
PJ2
93
PJ3
SIN1
PJ3
94
PJ4
SOT1
PJ4
95
PJ5
SCK1
PJ5
PJ2
P : Previous
Output
PJ3
Output
state held Previous Hi-Z/ Normal Normal
Hi-Z
PJ4
F : Normal state held input 0 operation operation
Input ready
PJ5
operation
fixed
96
PJ6
PPG0
PJ6
PJ6
97
PJ7
TRG0
PJ7
PJ7
98
PH0
TIN0
PH0
99
PH1 TIN1/PPG3 PH1
TIN2/
100 PH2
PH2
TRG3
PH0
P : Previous
Output
Output
PH1
state held Previous Hi-Z/ Normal Normal
Hi-Z
F : Normal state held input 0 operation operation
PH2
Input ready
operation
fixed
103 PB0 DREQ0
PB0
PB0
104 PB1 DACK0
PB1
PB1
105 PB2 DEOP0
PB2
PB2
106 PB3 DREQ1
PB3
DACK1/
107 PB4
PB4
TRG1
DEOP1/
108 PB5
PB5
PPG1
PB3
P : Previous
Output
Output
state held Previous Hi-Z/ Normal Normal
PB4
Hi-Z
F : Normal state held input 0 operation operation
Input ready
operation
fixed
PB5
109
PB6
IOWR
PB6
PB6
110 PB7
IORD
PB7
PB7
122 PA0
CS0
CS0
CS0
123 PA1
CS1
CS1
124 PA2
CS2
CS2
125 PA3
CS3
CS3
126 PA4 CS4/TRG2 CS4
127 PA5 CS5/PPG2 CS5
128 PA6
CS6
CS6
CS1
F:
F:
CS2
SREN=0 SREN=0 :
CS3
Output : H output H output
H output H output H output
CS4
Hi-Z SREN=1 SREN=1 :
CS5
: Output Output
CS6
Hi-Z
Hi-Z
129 PA7
CS7
CS7
CS7
132 to
139
142 to
144
P00 to
P07
P10 to
P12
D00 to D07
D08 to D10
P00 to P07
P10 to P12
P00 to P07
P10 to P12
Output Hi-
Z
Input ready
P : Previous
state held
F : Output
held or Hi-Z
P : Previ-
ous state
held
F : Output
held or
Hi-Z
Output
Hi-Z/
input 0
fixed
Output
Hi-Z
Output
Hi-Z
P : General-purpose port selected, F : Specified function selected
* : The following port’s function can be used on only MB91302A and MB91V301A, SDA0, SCL0,
SDA1, SCL1 of 68 to 71 pin, ICU0 to ICU3, FRCK of 81 to 85 pin.
Note : The bus width is determined after a mode vector fetch.
The bus width at initialization time is 8 bits.
562