MB91301A Datasheet, PDF (436/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

CHAPTER 14 DMA CONTROLLER (DMAC)
14.3.7 CPU Control
When a DMA transfer request is accepted, DMA issues a transfer request to the bus
controller.
The bus controller passes the right to use the internal bus to DMA at a break in bus
operation and DMA transfer starts.
I DMA Transfer and Interrupts
• During DMA transfer, interrupts are generally not accepted until the transfer ends.
• If a DMA transfer request occurs during interrupt processing, the transfer request is accepted
and interrupt processing is stopped until the transfer is completed.
• If, as an exception, an NMI request or an interrupt request with a higher level than the hold
suppress level set by the interrupt controller occurs, DMAC temporarily cancels the transfer
request via the bus controller at a transfer unit boundary (one block) to temporarily stop the
transfer until the interrupt request is cleared. In the meantime, the transfer request is
retained internally. After the interrupt request is cleared, DMAC reissues a transfer request to
the bus controller to acquire the right to use the bus and then restarts DMA transfer.
I Suppressing DMA
When an interrupt source with a higher priority occurs during DMA transfer, an FR family device
interrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid
as long as there are any interrupt requests. When all interrupt sources are cleared, the
suppression feature no longer works and the DMA transfer is restarted by the interrupt
processing routine. Thus, if you want to suppress restart of DMA transfer after clearing interrupt
sources in the interrupt source processing routine at a level that interrupts DMA transfer, use
the DMA suppress function. The DMA suppress function can be activated by writing any value
other than 0 to the DMAH[3:0] bits of the DMA all-channel control register and can be stopped
by writing 0 to these bits.
This function is mainly used in the interrupt processing routines. Before the interrupt sources in
an interrupt processing routine are cleared, the DMA suppress register is incremented by 1. If
this is done, then no DMA transfer is performed. After interrupt processing, decrement the
DMAH[3:0] bits by 1 before returning. If multiple interrupts have occurred, DMA transfer
continues to be suppressed since the DMAH[3:0] bits are not 0 yet. If a single interrupt has
occurred, the DMAH[3:0] bits become 0. DMA requests are then enabled immediately.
Note:
• Since the register has only four bits, this function cannot be used for multiple interrupts
exceeding 15 levels.
• Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than
other interrupt levels.
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