MB91301A Datasheet, PDF (455/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

CHAPTER 14 DMA CONTROLLER (DMAC)
14.6.1 Input Timing of the DREQx Pin
The DREQx pin is a DMA start request signal. If the pin is also used as a port, enable
the DREQ input using the PFR register. This section shows the input timing of the
DREQx pin.
I Timing of Transfer Other Than Demand Transfer
For transfer other than demand transfer, set the DMA start source to edge detection. Although
there is no rule for rise/fall timing, use three or more clock cycles as the holding time the DREQ
signal. To make another transfer request, enter the request after the DMA transfer is completed
(make a request after DEOP is output).
If a request is made before DEOP is output, it may be ignored.
Figure 14.6-1 "Timing Chart for Transfer Other Than the Demand Transfer" shows the timing
chart for transfer other than demand transfer.
Figure 14.6-1 Timing Chart for Transfer Other Than the Demand Transfer
When a DREQ edge is requested (for 2-cycle transfer)
MCLK
DREQ
A24 to 0
RD
WR
DEOP
#RD1 #WR1 #RD2 #WR2
CPU operation
MAD transfer
CPU
3 or more cycles
The next request must be after DEOP output
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