MB91301A Datasheet, PDF (226/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

CHAPTER 4 EXTERNAL BUS INTERFACE
4.5.6 External Wait Cycle
This section shows the operation timing for the external wait cycle.
I External Wait Cycle Timing
Figure 4.5-6 "Timing Chart for the External Wait Cycle" shows the operation timing for (TYP3-
0=0001_B, AWR=2008_H).
Figure 4.5-6 Timing Chart for the External Wait Cycle
Basic cycle 2 auto-wait cycles Wait cycle by RDY
MCLK
A[31:0]
AS
CSn
RD
D[31:0]
WRn
D[31:0]
RDY
Release
Wait
Setting 1 for the TYP0 bit of the ACR register and enabling the external RDY input pin enables
external wait cycles to be inserted.
In Figure 4.5 - 6, the oblique - lined portion of the RDY pin is invalid because the wait based on
the automatic wait cycle remains in effect.
The value at the RDY input pin is evaluated from the last automatic wait cycle on.
Once a wait cycle is completed, the value at the PDY input pin remains invalid until the next
access cycle is started.
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