MB91301A Datasheet, PDF (115/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

CHAPTER 3 CPU AND CONTROL UNITS
I Watchdog Reset
Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5_H/
5A_H is written to the watchdog reset postpone register (WPR) within the cycle specified in Bits 9
and 8 (WT1 and WT0 bits) in the RSRR, a watchdog reset request occurs.
A watchdog reset request is a settings initialization reset (INIT) request. If, after the request is
accepted, a settings initialization reset (INIT) occurs or an operation initialization reset (RST)
occurs, the watchdog reset request is cleared.
If a settings initialization reset (INIT) is generated due to a watchdog reset request, Bit 13
(WDOG bit) in the reset source register (RSRR) is set.
Note that, if a settings initialization reset (INIT) is generated due to a watchdog reset request,
the oscillation stabilization wait time is not initialized.
• Reset source: Setting cycle of the watchdog timer elapses
• Source of clearing: Generation of a settings initialization reset (INIT) or an operation
initialization reset (RST)
• Reset level: Settings initialization reset (INIT)
• Corresponding flag: Bit 13 (WDOG)
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