MB91301A Datasheet, PDF (228/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

CHAPTER 4 EXTERNAL BUS INTERFACE
• If synchronous write enable output is used, the following restrictions apply:
Do not set the following additional wait because the timing for synchronous write enable
output becomes meaningless:
- CS -> RD/WRn setup (Always write 0 to the W01 bit of AWR)
- First wait cycle setting (Always write 0000 to bits W15-W12 of AWR)
Do not set the following access types (TYPE3-0 bits (Bits 3-0) in the ACR register) because
the timing for synchronous write enable output becomes meaningless:
- Multiplex bus setting (Always write 0 to the TYPE2 bit of ACR)
- RDY input enable setting (Always write 0 to the TYPE0 bit of ACR)
Always set the burst length to "1" (BST1 to 0 bit = 0) for the synchronous write enable output
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