MB91301A Datasheet, PDF (194/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

CHAPTER 4 EXTERNAL BUS INTERFACE
4.2.10 Refresh Control Register (RCR)
This section describes the bit configuration and functions of the refresh control
register (RCR).
I Structure of the Refresh Control Register (RCR)
The refresh control register (RCR) is used to make various refresh control settings for SDRAM.
The setting of this register is meaningless as long as SDRAM control is not set for any area, in
that case the register value must not be updated from the initial state.
When read by a Read - modify - Write instruction, the SELF, RRLD, and PON bits always return
to 0.
Figure 4.2-10 shows the bit configuration of the refresh control register (RCR).
Figure 4.2-10 Structure of the Refresh Control Register (RCR)
RCRH bit
Address 0000 0684_H
RCRL bit
Address _{0000 0685H}
31
SELF
W/R
Initial value
30
29
28
27
26
25
24
00XXXXXXB(INIT)
RRLD RFINT5 RFINT4 RFINT3 RFINT2 RFINT1 RFINT0
00XXXXXXB(RST)
W/R W/R W/R W/R W/R W/R ^W/R
23
22
BRST RFC2
W/R W/R
21 20
RFC1 RFC0
W/R W/R
19
PON
W/R
18
TRC2
W/R
17
TRC1
W/R
16
TRC0 ^{XXXX0XXXB(INIT)}
XXXX0XXXB(RST)
W/R
178