MB91301A Datasheet, PDF (340/622 Pages) Fujitsu Component Limited. – 32-BIT MICROCONTROLLER

CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
I External Interrupt Request Level
If the request level is an edge request, a pulse width of at least three machine cycles (peripheral
clock machine cycles) is required to detect an edge.
If the request input level is a level setting and request input arrives from outside and is then
cancelled, the request to the interrupt controller remains active because a source holding circuit
exists internally.
The interrupt source register must be cleared to cancel a request to the interrupt controller.
Figure 9.3-2 "Clearing the Source Holding Circuit when a Level is Set" shows clearing of the
source holding circuit when a level is set. Figure 9.3-3 "Interrupt Source and Interrupt Request
to Interrupt Controller when Interrupts are Enabled" shows an interrupt source and an interrupt
request to the interrupt controller when interrupts are enabled.
Interrupt input
Figure 9.3-2 Clearing the Source Holding Circuit when a Level is Set
Level detection
Source F/F
(Source holding circuit)
Enable gate
Interrupt controller
Holds a source while it is not cleared
Figure 9.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled
Interrupt input
H level
Interrupt request to
interrupt controller
Becomes inactive when source F/F is cleared
I NMI
An NMI has the highest level among the user interrupts and usually cannot be masked.
However, as an exception, if an NMI is activated before it is set in ILM, the CPU dose not accept
the NMI but only detects the NMI source. The NMI source is then held until ILM is set to the
level that allows the NMI to be accepted. For this reason, before using an NMI, be sure to set
ILM to 16 or more after a reset.
As the internal source flag of NMI cannot be accessed by the CPU, the NMI pin must be
maintained at the level "H" after a reset.
An NMI is accepted under the following conditions:
• Normal: falling edge
• STOP mode: L level
An NMI can be used to clear stop mode. Inputting the L level in the stop state clears the stop
state and causes the oscillation stabilization wait time to start. To perform NMI processing after
clearing the stop state, maintain the NMI pin at the L level and return it to the H level in the NMI
processing routine.
The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an
interrupt for the NMI itself is accepted or a reset occurs. Note that this bit is not readable or
writable.
Figure 9.3-4 "NMI Request Detector" shows the NMI request detector.
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