MB82DBS08164D-70L Datasheet, PDF (5/60 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word x 16 bit) Mobile Phone Application Specific Memory

MB82DBS08164D-70L
2. Synchronous Operation (Burst Mode)
Mode
CE2 CE1 CLK ADV WE OE LB UB A22 to A0 DQ15 to DQ0
WAIT
Standby(Deselect)
H X X XXXX
X
High-Z High-Z
Start Address Latch*¹
*³
L X*⁴ X*⁶
Valid*⁸ High-Z*⁹
Output
Invalid
Advance Burst Read to
Next Address*¹
Burst Read
Suspend*¹
H
Advance Burst Write to
Next Address*¹
Burst Write Suspend*¹
*³
L *³
*³
*³
L
H
H
X*⁷ X*⁷
H ^L*5
X
H
H*⁵
Output
Valid*¹⁰
High-Z
Input
Valid*¹¹
Input
Invalid
Output
Valid
High*¹²
High*¹³
High*¹²
Terminate Burst Read
X
HX
High-Z High-Z
Terminate Burst Write
X
XH
High-Z High-Z
Power Down*²
L X X X XXXX
X
High-Z High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, = valid edge, High-Z = High impedance
*1 : Should not be kept this logic condition longer than 8 μs.
*2 : Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program.
Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details.
*3 : CLK must be started and stable prior to memory access.
*4 : Can be VIH for the burst write operation in "WE Level Control" mode but must be VIL for the burst write
operation in "WE Single Clock Pulse Control" mode. WE must be VIH for the burst read operation.
*5 : When device is operating in "WE Single Clock Pulse Control" mode, WE is a “don't care” once write operation
is determined by WE Low Pulse at the beginning of write access together with address latching. Burst write
suspend feature is not supported in "WE Single Clock Pulse Control" mode.
*6 : Can be VIL for the burst read operation but must be VIH for the burst write operation.
*7 : Can be either VIL or VIH. During burst write operation, byte write control by LB and UB can be performed at
each clock cycle. During read operation, LB and UB must be valid before read operation is initiated. And once
LB and UB input levels are determined, they must not be changed until the end of burst read.
*8 : Once a valid address is determined, the input address must not be changed during ADV = L.
*9 : If OE = L, data output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L,
data input is Invalid. If OE = WE = H, data output is High-Z.
*10 : Data output is either Valid or High-Z depending on the level of LB and UB input.
*11 : Data input is either Valid or Invalid depending on the level of LB and UB input.
*12 : Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in
"■FUNCTIONAL DESCRIPTION" for the details.
*13 : WAIT output is driven in High level during burst write operation.
DS05-11454-1E
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