MB82DBS08164D-70L Datasheet, PDF (13/60 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word x 16 bit) Mobile Phone Application Specific Memory

MB82DBS08164D-70L
• Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through CR Set sequence after power-up. Once
specific RL is set through CR Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1.
The burst operation is always started after the fixed latency with respect to Read Latency set in CR.
CLK
Address
ADV
CE1
OE or WE
DQ ^[Output]
WAIT
DQ ^[Input]
WAIT
DQ ^[Output]
WAIT
DQ ^[Input]
WAIT
DQ ^[Output]
WAIT
DQ ^[Input]
WAIT
0
1
2
3
4
5
6
7
Valid address
RL = 4
High-Z
High-Z
RL = 5
High-Z
High-Z
RL = 6
High-Z
High-Z
Q1
Q2
Q3
Q4
D1
D2
D3
D4
D5
Q1
Q2
Q3
D1
D2
D3
D4
Q1
Q2
D1
D2
D3
DS05-11454-1E
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