MB82DBS08164D-70L Datasheet, PDF (20/60 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word x 16 bit) Mobile Phone Application Specific Memory

MB82DBS08164D-70L
(2) Asynchronous Write Operation
Parameter
Write Cycle Time
Address Setup Time to ADV Low
Address Setup Time
ADV Low Pulse Width
ADV High Pulse Width
Address Hold Time from ADV High
CE1 Write Pulse Width
WE Write Pulse Width
LB, UB Write Pulse Width
LB, UB Byte Mask Setup Time
LB, UB Byte Mask Hold Time
Write Recovery Time
CE1 High Pulse Width
WE High Pulse Width
LB, UB High Pulse Width
Data Setup Time
Data Hold Time
OE High to CE1 Low Setup Time for Write
OE High to Address Setup Time for Write
(At recommended operating conditions unless otherwise noted)
Symbol
Value
Min
Max
Unit Notes
tWC
70
1000
ns *1, *2
tASVL
−5
⎯
ns *3
tAS
0
⎯
ns
tVPL
7
⎯
ns *3
tVPH
10
⎯
ns
tAHV
5
⎯
ns
tCW
45
⎯
ns *2, *4
tWP
45
⎯
ns *2, *4
tBW
45
⎯
ns *2, *4
tBS
−5
⎯
ns *5
tBH
−5
⎯
ns *6
tWR
0
⎯
ns *2, *7
tCP
10
⎯
ns
tWHP
10
1000
ns *8
tBHP
10
1000
ns *8
tDS
15
⎯
ns
tDH
0
⎯
ns
tOHCL
−5
⎯
ns *9
tOES
0
⎯
ns *10
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : The sum of write pulse width (tCW, tWP or tBW) and actual write recovery time (tWR) must be equal or greater than
specified minimum tWC.
*3 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and
tASVL must be equal or greater than the specified minimum value of tVPL.
*4 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last.
*5 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE
whichever occurs last.
*6 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
whichever occurs first.
*7 : Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first.
*8 : Maximum specification of tWHP and tBHP are applicable to Output Disable mode when CE = L, WE = OE = H
after write operation. Refer to “(7) Asynchronous Write Timing 2 (WE Control)” in “ ■ TIMING DIAGRAMS”.
*9 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns
after CE1 is brought to Low.
*10 : If OE is Low after a new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before a new address becomes valid.
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DS05-11454-1E