MB82DBS08164D-70L Datasheet, PDF (12/60 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word x 16 bit) Mobile Phone Application Specific Memory

MB82DBS08164D-70L
• ADV Input Function
The ADV is input signal to latch the valid address. It is applicable to the synchronous operation as well as
asynchronous operation. ADV input is active during CE1 = L and CE1 = H disables ADV input.
During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to
High after the valid address latch, it is inhibited to bring ADV Low until the end of burst or until the burst operation
is terminated. ADV Low pulse is mandatory for the synchronous burst read/write operation mode to latch the
valid address input.
During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during
asynchronous operations and it is not necessary to control ADV to High.
• WAIT Output Function
The WAIT is output signal to indicate the data bus status when the device is operating in the synchronous burst
mode.
During burst read operation, WAIT output is enabled after specified time duration from CE1 = L. WAIT output
Low indicates data output at next clock cycle is invalid, and WAIT output becomes High one clock cycle prior to
valid data output. During OE read suspend, WAIT output doesn’t indicate the data bus status but carries the
same level from previous clock cycle (kept High).
During burst write operation, WAIT output is enabled after specified time duration from CE1 = L. WAIT output to
High level after specified time duration from WE = L or CE1 = L whichever occurs last and kept High for entire
write cycles including WE write suspend. The actual write data latching starts on the appropriate clock edge
with respect to Read Latency, and Burst Length. During WE write suspend, WAIT output doesn’t indicate the
data bus status but carries the same level from previous clock cycle (kept High).
This device doesn’t incur additional output delay against internal refresh operation. Therefore, the burst operation
is always started after the fixed latency with respect to Read Latency. And there is no waiting cycle asserted in
the middle of burst operation except for the burst read or write suspend by OE brought to High or WE brought
to High. Thus, once WAIT output is enabled and brought to High, WAIT output keeps High level until the end of
burst or until the burst operation is terminated.
When the device is operating in the asynchronous mode, WAIT output is always in High Impedance.
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DS05-11454-1E