MB82DBS08164D-70L Datasheet, PDF (21/60 Pages) Fujitsu Component Limited. – 128 M Bit (8 M word x 16 bit) Mobile Phone Application Specific Memory

MB82DBS08164D-70L
(3) Synchronous Operation - Clock Input (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit Notes
RL = 6
13
⎯
ns *1
Clock Period
RL = 5
tCK
15
⎯
ns *1
RL = 4
18
⎯
ns *1
Clock High Time
tCKH
3
⎯
ns
Clock Low Time
tCKL
3
⎯
ns
Clock Transition Time
tCKT
⎯
1.5
ns *2
*1 : Clock period is defined between valid clock edges.
*2 : Clock transition time is defined between VIH (Min) and VIL (Max)
(4) Synchronous Operation - Address Latch (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Parameter
Symbol
Value
Min
Max
Unit Notes
Address Setup Time to CLK
tASCK
3
⎯
ns *1
Address Hold Time from CLK
tCKAH
1
⎯
ns *1
ADV Low Pulse Width
tVPL
7
⎯
ns *2
RL = 6
3
⎯
ADV Low Setup Time to CLK
tVSCK
ns *1
RL = 4, 5
5
⎯
RL = 6
3
⎯
CE1 Low Setup Time to CLK
tCLCK
ns *1
RL = 4, 5
5
⎯
ADV Low Hold Time from CLK
tCKVH
1
⎯
ns *1
CE1 High Hold Time from CLK
tCKCH
1
⎯
ns *3
*1 : Applicable to the 1st rising clock edge.
*2 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
*3 : Applicable to the positive clock edge before address latching.
DS05-11454-1E
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