MB39C011APFT-G-BND-ERE1 Datasheet, PDF (41/53 Pages) Cypress Semiconductor – 2 ch DC/DC Converter IC with Synchronous Rectification

MB39C011A
20. PCB Layout
Consider the following points when designing the PCB layout :
Make the input capacitor (Cin), SW FET, Fly-back diode (SBD), coil (L), and output capacitor (Cout) connections on the surface
as much as possible, and avoid making the connections with the through-holes.
Take the most care with the loop consisting of the input capacitor (Cin), SW FET, and Fly-back diode (SBD), and make the
current loop as small as possible.
Create through-hole directly next to the GND pins of the input capacitor (Cin), SW FET, Fly-back diode (SBD), and output
capacitor (Cout), and connect these to the SW system GND inner layer.
Large currents flow momentarily through the wiring of the OUTx-x pins that are connected to the SW FET gates. Use a wiring
width of about 0.8 mm as a guide, and make the wiring as short as possible.
Arrange the bypass capacitors that are connected to the VCC, VB, and VH pins (pins 1, 4, and 16) near the pins as possible.
Furthermore, connect the GND pin of the VCC and VB by-pass capacitor with a nearest GND pin of the IC. (Create a
through-hole directly next to the GND pin of the IC (pin 12) and the GND pins of the bypass capacitors to reinforce the
connection to the inner ground layer).
The wiring for the -INE1, -INE2, FB1, FB2, and RT pins (pins 7, 10, 6, 11, and 5) is sensitive to noise and should be made as
short as possible. Furthermore, the feedback line from the output (V_O) should be kept as far away from SW system components
as possible.
Create as much ground plane on the side where the IC is mounted as possible. To prevent creating a large current path to the
control system GND, connect this to the PGND (SW system GND) at a single point.
Document Number: 002-08369 Rev. *A
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