MB39C011APFT-G-BND-ERE1 Datasheet, PDF (14/53 Pages) Cypress Semiconductor – 2 ch DC/DC Converter IC with Synchronous Rectification

Soft-start circuit
Vo
R1
R2
(-INE2)
10
-INE1
7
CSCP
CSCP1
8
(CSCP2) ₉
FB1 ₆
(FB2) ₁₁
VB
Ic1
Ics
MB39C011A
Ic1[A] 3.710^5/R_T [k]
Ic2
Ic2[A] 1.710^5/R_T [k]
R_T : Timing resistor
L priority
Error Amp
(1.0 V)
UVLO
8.2.2 Timer-Latch Short-Circuit Protection Circuit
Each channel has a short-circuit detection comparator (SCP Comp1 and Comp2) that constantly compares the output level of the
error amplifier against the reference voltage. While the DC/DC converter load conditions remain stable, the error amplifier output
does not change and the short-circuit protection comparator remains in an equilibrium state. At this time, the CSCP1 and CSCP2
pins (pins 8 and 9) maintain the voltage from when the soft-start finished (about 1.3 V). If the output voltage of the DC/DC converter
falls drastically due to a short-circuit or other load conditions, the output voltage of the error amplifier rises 1.9 V or more, and the
external CSCP1 and CSCP2 capacitors are further charged. When the CSCP1 or CSCP2 capacitors are charged to about 2.0 V,
a latch is set that turns off the external P-ch/N-ch MOSFETs (dead time is set to 100%). At this time, the latch input is closed and
the CSCP1 and CSCP2 pins (pins 8 and 9) are held at the “L” level. Once the protection circuit has been activated, it can be reset
by allowing the VB pin (pin 4) voltage to 3.8 V (minimum) or loss by turning the power off and on again.
t_CSCP 0.019 CSCP R_T
t_CSCP :Short-circuit detection time [s]
CSCP :Capacitance of CSCP pin [F]
R_T
:Timing resistance [k]
Document Number: 002-08369 Rev. *A
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