MB39C011APFT-G-BND-ERE1 Datasheet, PDF (26/53 Pages) Cypress Semiconductor – 2 ch DC/DC Converter IC with Synchronous Rectification

MB39C011A
14. Design Of Phase Compensation Circuit
14.1 Phase compensation circuit when low ESR capacitor is used as output
capacitor
When a low-ESR capacitor such as a ceramic capacitor is used as the output capacitor, it becomes easy to vibrate for a phase
delay of the 180° to be generated due to the resonant frequency of the LC. In this case, it is common to use a phase compensation
circuit that can advance the phase, such as a 2-pole/2-zero circuit.
2-pole/2-zero phase compensation circuit
VO1,VO2
R3
R1
Rc Cc
C1
-
-INE1,-INE2
R2
+ ^FB1,FB2
Error
Vref ^Amp1,Amp2
To PWM
Comp.1,2
Set the R3, Rc, C1, and Cc constants in the phase compensation circuit by using the following formula as a guide. As for frequency
(f_CO) of crossover, in which the band width of the control loop of DC/DC is shown, height is excellent in the rapid response. However,
vibration may be generated due to an insufficient phase margin. Although the
crossover frequency (f_CO) can be set to any value, the maximum value must be 1/2 of the oscillation frequency (f_OSC), or 1/5 of
the oscillation frequency (f_OSC) as preferable. Furthermore, the crossover frequency (f_CO) should be set such that the phase margin
is a minimum of 30°, or more than 45° as preferable.
Document Number: 002-08369 Rev. *A
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