MB39C011APFT-G-BND-ERE1 Datasheet, PDF (16/53 Pages) Cypress Semiconductor – 2 ch DC/DC Converter IC with Synchronous Rectification

Soft-start and short-circuit protection timing chart
CSCP voltage
2.0 V
Soft-start time
ts
MB39C011A
Short-circuit detection time
tcscp
1.3 V
1.0 V
Output short
Output short
t
(1)
(2) (3)
(4)
(5)
(6)
(7)
1. When the CTL pin (pin 13) is set to the “H” level and the IC becomes active, the voltages of the CSCP1 and CSCP2 pins (pins
8 and 9) rise due to the capacitors attached externally to the CSCP1 and CSCP2 pins (pins 8 and 9) being charged. During
this time, Error Amp1 and Error Amp2 are controlled by the CSCP1 and CSCP2 pins (pins 8 and 9) and the -INE1 and -INE2
pins (pins 7 and 10) inputs, thus performing a soft-start.
2. When the CSCP1 and CSCP2 pins (pins 8 and 9) reach 1 V or more, Error Amp1 and Error Amp2 become controlled by the
internal reference voltage (1 V) and the -INE1 and -INE2 pin (pins 7 and 10) inputs, and the output voltage is held at a constant
level.
3. The CSCP1 and CSCP2 pins (pins 8 and 9) are clamped to about 1.3 V.
4. When there is a short circuit in the load and the error amplifier output becomes 1.9 V or more, the short-circuit protection
comparator (SCP Comp.) is activated and the CSCP1 and CSCP2 capacitors are charged further.
5.
If the short-circuit in the load is cleared within
9) return to the clamping voltage of about 1.3
the
V.
short-circuit
detection
time
t_CSCP,
the
CSCP1
and
CSCP2
pins
(pins
8
and
6. When there is a short-circuit in the load and the error amplifier output becomes 1.9 V or more, the short-circuit protection
comparator (SCP Comp.) is activated and the CSCP1 and CSCP2 capacitors are charged further.
7.
The latch is set when
P-ch/N-ch are turned
the
off,
load
and
short-circuit is not released even if short-circuit detection time
the CSCP1,CSCP2 pins (pins 8 and 9) are hold at “L” level.
t_CSCP
passes,
external
MOS
FET
Document Number: 002-08369 Rev. *A
Page 16 of 53