MB39C313 Datasheet, PDF (32/52 Pages) Fujitsu Component Limited. – 4ch System Power Management IC for LCD Panel

MB39C313
(4) PCB Layout Recommendation
PCB layout is significant for power supply design. Poor layout would result in generating unwanted voltage
and current spikes. This will not only affect DC output voltage, but also radiate EMI to adjacent equipment.
Sufficient grounding and minimize parasitic inductance can reduce DC/DC converter switching spike noise.
The following list of rules should be followed when designing power PCB layout
1. Place tracks on the Top Layer and avoid using via or through hole; particularly for nets, such as Input
Capacitor (Cin), Inductor (L) and Output Capacitor (Cout).
2. Place the Input Capacitor (Cin) close to the IC, so as to reduce loop current.
3. Place the Schottky diodes close to the SW and SWB respectively, so as to reduce spike noise.
4. Strengthen the ground connection of Input Capacitor (Cin), and Output Capacitor (Cout) with the ground
planes. This can be done by placing via holes next to the GND terminals of these components.
5. Place the Schottky Diode and Pumping Capacitor of the two charge pump channels close to IC.
6. The Decoupling Capacitor should be placed near to IC pin of VINB and AVIN. Separate track is required
for AVIN and VINB. The GND terminal of AVIN should be placed close to the GND terminal of IC. (Via
holes should be placed near to the GND terminals of IC and Capacitors. The connections to internal
ground plane should be strengthened at these points.)
7. Feedback paths (i.e. FBB, FB, FBN, FBP) are very sensitive to noise, thus the track should be as short
as possible at these terminals. The Output (Vo) feedback line should be placed away from switching
components and tracks. Particularly DRN and FBN of the negative charge pump. Use the FREQ pin to
separate these two tracks. Similarly, the FBB and SWB can be separated by the EN1 track. Because
EN1, EN2 and FREQ are less susceptible to noise.
8. Place wide and short track to connect Boost Converter Output and OS pin.
9. The two ground planes GND and PGND are intersect at the IC thermal pad only.
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DS04–27267–1E