MB39C313 Datasheet, PDF (30/52 Pages) Fujitsu Component Limited. – 4ch System Power Management IC for LCD Panel

MB39C313
(3) Pumping Capacitor and Output Capacitor Selection
Selection of pumping capacitor and output capacitor are similar to Positive Charge Pump design.
For −5 V output, ΔVDRN = −VGL − Vdiode = −5 V − 0.4 V = −5.4 V. The pumping capacitor and output filtering
capacitor can be estimated for required application.
Fast input voltage change at power off causes under-shoot (becomes more negative) at Negative Charge
Pump output. This under shoot can be reduced by increasing the output capacitance to pumping capacitance
ratio. The power off coupling voltage is VIN − | ΔVDRN |. The coupling effect can be estimated as below:
ΔVunder-shot = (VIN − | ΔVDRN |) = ×
Cpump-cap
Cpump-cap + Coutpu-cap
Where:
ΔVunder − shot = under-shot voltage by power off coupling.
ΔVDRN = pumping clock voltage
Cpump-cap = pumping capacitance
Coutput-cap = output capacitance
In real application, the power off coupling should be negligible due to large loading gate capacitance on panel.
(4) REF Capacitor Selection
REF pin capacitor is used for defining the low frequency gain of reference voltage buffer. 220 nF capacitor
is used for stability and performance. Change of capacitance is NOT recommended.
(5) DLY Capacitor Selection
Refer to “Power Up Sequence” section, power up sequence timing is set by capacitor at DLY1 and DLY2
pins. The delay capacitor can be estimated by following equation.
Cdelay =
5.5 μA × tdelay
VREF
Where:
tdelay = delay time
Cdelay = capacitor connected to DLY-pin
VREF = 1.213 V
(6) Input capacitor Selection
It is recommended to use low ESR capacitor like ceramic capacitor for the input filtering. For AVIN terminal,
a 1 μF capacitance connected from AVIN to ground is needed. For the Buck converter, use minimum of two
22 μF ceramic capacitors connected from VINB pin to ground. For the Boost converter, minimum of one
22 μF ceramic capacitor connected from the inductor terminal to ground is recommended.
5. System Design Consideration
(1) Output Glitches when Very Slow Power up Time
A very slow power up time may cause channel output glitches when input voltage across UVLO voltage.
Due to slow rise of input voltage at UVLO threshold, the UVLO is easily triggered with switching noise. This
undesired UVLO activation will cause glitches at output when channel is loaded.
The main reason is due to the input voltage drop by sudden current draw when channel startup. For maximum
output loading, 0.1 Ω equivalent series resistance of power line is able to cause 0.3 V voltage drop. Consider
UVLO hysteresis voltage and its response time with margin. For typical setting (VIN = 12 V, VLogic = 3.3 V/
1.5 A and other channels without load, 0.1 Ω source resistance), it is suggested less than 167 ms input
voltage ramp time to avoid such glitches. Refer to "■ TYPICAL APPLICATION CIRCUIT" for typical appli-
cation setting.
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DS04–27267–1E