MC9S08AC16 Datasheet, PDF (95/338 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

6.7.5 Port C I/O Registers (PTCD and PTCDD)
Port C parallel I/O function is controlled by the registers listed below.
Chapter 6 Parallel Input/Output
7
R
0
W
6
5
4
3
2
R
PTCD5
PTCD4
PTCD3
PTCD2
Reset
0
0
0
0
0
0
Figure 6-20. Port C Data Register (PTCD)¹
1 _{Bit 6 is a reserved bit that must always be written to 0.}
1
PTCD1
0
0
PTCD0
0
Table 6-11. PTCD Register Field Descriptions
Field
Description
5:0
PTCD[5:0]
Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7
R
0
W
6
5
4
3
2
R
PTCDD5 PTCDD4 PTCDD3 PTCDD2
Reset
0
0
0
0
0
0
Figure 6-21. Data Direction for Port C (PTCDD)¹
1 _{Bit 6 is a reserved bit that must always be written to 0.}
1
PTCDD1
0
0
PTCDD0
0
Table 6-12. PTCDD Register Field Descriptions
Field
Description
5:0
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCDD[5:0] PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
MC9S08AC16 Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
95