MC9S08AC16 Datasheet, PDF (87/338 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
the external oscillator is enabled, PTG5 and PTG6 function as oscillator pins. In this case the associated
parallel I/O and pin control registers have no control of the pins.
Refer to Chapter 8, “Internal Clock Generator (S08ICGV4)” for more information about using port G pins
as XTAL and EXTAL pins.
Refer to Chapter 9, “Keyboard Interrupt (S08KBIV1)” for more information about using port G pins as
keyboard inputs.
6.4 Parallel I/O Control
Reading and writing of parallel I/O is done through the port data registers. The direction, input or output,
is controlled through the port data direction registers. The parallel I/O port function for an individual pin
is illustrated in the block diagram below.
PTxDDn
DQ
Output Enable
PTxDn
DQ
Output Data
Port Read
Data
1
0
Synchronizer
Input Data
BUSCLK
Figure 6-9. Parallel I/O Block Diagram
The data direction control bits determine whether the pin output driver is enabled, and they control what
is read for port data register reads. Each port pin has a data direction register bit. When PTxDDn = 0, the
corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn = 1, the
corresponding pin is an output and reads of PTxD return the last value written to the port data register.
When a peripheral module or system function is in control of a port pin, the data direction register bit still
controls what is returned for reads of the port data register, even though the peripheral system has
overriding control of the actual pin direction.
MC9S08AC16 Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
87