MC9S08AC16 Datasheet, PDF (84/338 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 6 Parallel Input/Output
6.3.2 Port B
Port B
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin: R
PTB3/ PTB2/
R
R
R TPM3CH0/ TPM3CH1/
AD1P3 AD1P2
Figure 6-3. Port B Pin Names
PTB1/
AD1P1
PTB0/
AD1P0
Port B pins are general-purpose I/O pins. Parallel I/O function is controlled by the port B data (PTBD) and
data direction (PTBDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTBPE), slew rate control (PTBSE), and drive strength select (PTBDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port B general-purpose I/O are shared with the ADC and TPM3 timer channels. Any pin enabled as an
ADC input will have the general-purpose I/O function disabled. When any TPM3 function is enabled, the
direction (input or output) is controlled by the TPM3 and not by the data direction register of the parallel
I/O port. Refer to Chapter 10, “Timer/PWM (S08TPMV3),” for more information about using port B pins
as TPM channels. Refer to Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” for more
information about using port B as analog inputs.
6.3.3 Port C
Port C
Bit 7
6
5
3
3
2
1
Bit 0
MCU Pin: 0
R
PTC5/
RxD2
PTC4
PTC3/
TxD2
Figure 6-4. Port C Pin Names
PTC2/
MCLK
PTC1/
SDA1
PTC0/
SCL1
Port C pins are general-purpose I/O pins. Parallel I/O function is controlled by the port C data (PTCD) and
data direction (PTCDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTCPE), slew rate control (PTCSE), and drive strength select (PTCDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port C general-purpose I/O is shared with SCI2, IIC, and MCLK. When any shared function is enabled,
the direction, input or output, is controlled by the shared function and not by the data direction register of
the parallel I/O port. Also, for pins which are configured as outputs by the shared function, the output data
is controlled by the shared function and not by the port data register.
Refer to Chapter 11, “Serial Communications Interface (S08SCIV4)” for more information about using
port C pins as SCI pins.
Refer to Chapter 13, “Inter-Integrated Circuit (S08IICV2)” for more information about using port C pins
as IIC pins.
Refer to Chapter 5, “Resets, Interrupts, and System Configuration” for more information about using
PTC2 as the MCLK pin.
MC9S08AC16 Series Data Sheet, Rev. 0
84
PRELIMINARY
Freescale Semiconductor