MC9S08AC16 Datasheet, PDF (85/338 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

6.3.4 Port D
Chapter 6 Parallel Input/Output
Port D
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin: R
PTD3/
R
R
R
AD1P11/
KBIP6
Figure 6-5. Port D Pin Names
PTD2/
AD1P10/
KBIP5
PTD1/
AD1P9
PTD0/
AD1P8
Port D pins are general-purpose I/O pins. Parallel I/O function is controlled by the port D data (PTDD) and
data direction (PTDDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTDPE), slew rate control (PTDSE), and drive strength select (PTDDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port D general-purpose I/O are shared with the ADC and KBI. When any of these shared functions is
enabled, the direction, input or output, is controlled by the shared function and not by the data direction
register of the parallel I/O port. When a pin is shared with both the ADC and a digital peripheral function,
the ADC has higher priority. For example, in the case that both the ADC and the KBI are configured to use
PTD7 then the pin is controlled by the ADC module.
Refer to Chapter 10, “Timer/PWM (S08TPMV3)” for more information about using port D pins as TPM
external clock inputs.
Refer to Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” for more information about using
port D pins as analog inputs.
Refer to Chapter 9, “Keyboard Interrupt (S08KBIV1)” for more information about using port D pins as
keyboard inputs.
6.3.5 Port E
Port E
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin:
PTE7/
SPSCK1
PTE6/
MOSI1
PTE5/
MISO1
PTE4/ PTE3/ PTE2/
SS1 TPM1CH1 TPM1CH0
Figure 6-6. Port E Pin Names
PTE1/
RxD1
PTE0/
TxD1
Port E pins are general-purpose I/O pins. Parallel I/O function is controlled by the port E data (PTED) and
data direction (PTEDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTEPE), slew rate control (PTESE), and drive strength select (PTEDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port E general-purpose I/O is shared with SCI1, SPI, and TPM1 timer channels. When any of these shared
functions is enabled, the direction, input or output, is controlled by the shared function and not by the data
direction register of the parallel I/O port. Also, for pins which are configured as outputs by the shared
function, the output data is controlled by the shared function and not by the port data register.
MC9S08AC16 Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
85