MC9S08AC16 Datasheet, PDF (60/338 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Chapter 4 Memory
4.6.4 FLASH Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT are copied from FLASH into FPROT. This
register can be read at any time. If FPDIS = 0, protection can be increased, i.e., a smaller value of FPS can
be written. If FPDIS = 1, writes do not change protection.
7
R
W
Reset
6
5
4
3
2
1
FPS⁽¹⁾
This register is loaded from nonvolatile location NVPROT during reset.
1 _{Background commands can be used to change the contents of these bits in FPROT.}
0
FPDIS⁽¹⁾
Figure 4-8. FLASH Protection Register (FPROT)
Table 4-11. FPROT Register Field Descriptions
Field
Description
7:1
FPS[7:1]
0
FPDIS
FLASH Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected
FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or
programmed.
FLASH Protection Disable
0 FLASH block specified by FPS[7:1] is block protected (program and erase not allowed).
1 No FLASH block is protected.
4.6.5 FLASH Status Register (FSTAT)
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
7
6
5
4
3
2
1
0
R
FCCF
0
FBLANK
0
0
FCBEF
FPVIOL FACCERR
W
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-9. FLASH Status Register (FSTAT)
MC9S08AC16 Series Data Sheet, Rev. 0
60
PRELIMINARY
Freescale Semiconductor