MC9S08AC16 Datasheet, PDF (73/338 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Field
3
ILAD
2
ICG
1
LVD
Chapter 5 Resets, Interrupts, and System Configuration
Table 5-4. SRS Register Field Descriptions (continued)
Description
Illegal Address — Reset was caused by an attempt to access a designated illegal address.
0 Reset not caused by an illegal address access.
1 Reset caused by an illegal address access.
Illegal address areas in the MC9S08AC16 are:
0x0470 - 0x17FF — Gap from end of RAM to start of high page registers
0x1860 - 0xBFFF — Gap from end of high page registers to start of Flash memory
Unused and reserved locations in register areas are not considered illegal addresses and do not trigger illegal
address resets.
Internal Clock Generation Module Reset — Reset was caused by an ICG module reset.
0 Reset not caused by ICG module.
1 Reset caused by ICG module.
Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage,
an LVD reset will occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.9.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
BDFR¹
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{BDFR is writable only through serial background debug commands, not from user programs.}
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
Table 5-5. SBDFR Register Field Descriptions
Field
0
BDFR
Description
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This
bit cannot be written from a user program.
MC9S08AC16 Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
73