MC9S08JM60_09 Datasheet, PDF (90/388 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
6.5.7 Port D I/O Registers (PTDD and PTDDD)
Port D parallel I/O function is controlled by the registers listed below.
R
W
Reset
7
PTDD7
0
6
PTDD6
5
PTDD5
4
PTDD4
3
PTDD3
2
PTDD2
0
0
0
0
0
Figure 6-17. Port D Data Register (PTDD)
1
PTDD1
0
0
PTDD0
0
Table 6-16. PTDD Register Field Descriptions
Field
Description
7:0
PTDD[7:0]
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
R
W
Reset
7
PTDDD7
0
6
PTDDD6
5
PTDDD5
4
PTDDD4
3
PTDDD3
2
PTDDD2
0
0
0
0
0
Figure 6-18. Data Direction for Port D (PTDDD)
1
PTDDD1
0
0
PTDDD0
0
Table 6-17. PTDDD Register Field Descriptions
Field
Description
7:0
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDDD[7:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
6.5.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)
In addition to the I/O control, port D pins are controlled by the registers listed below.
MC9S08JM60 Series Data Sheet, Rev. 3
90
Freescale Semiconductor