MC9S08JM60_09 Datasheet, PDF (74/388 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
Table 5-3. SRS Register Field Descriptions (continued)
Field
5
COP
4
ILOP
2
LOC
1
LVD
Description
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Loss-of-Clock Reset — Reset was caused by a loss of external clock.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
Low Voltage Detect — If the LVD is enable with the LVDRE or LVDSE bit is set, and the supply drops below the
LVD trip voltage, an LVD reset will occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.7.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
7
6
5
4
3
2
1
R
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{BDFR is writable only through serial background debug commands, not from user programs.}
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
0
0
BDFR¹
0
Table 5-4. SBDFR Register Field Descriptions
Field
0
BDFR
Description
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This
bit cannot be written from a user program.
5.7.4 System Options Register 1 (SOPT1)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
MC9S08JM60 Series Data Sheet, Rev. 3
74
Freescale Semiconductor