MC9S08JM60_09 Datasheet, PDF (39/388 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 3 Modes of Operation
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2
Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes.
Table 3-2. Stop Mode Behavior
Peripheral
Stop2
Mode
Stop3
CPU
Off
Standby
RAM
Standby
Standby
Flash
Off
Standby
Parallel Port Registers
ADC
ACMP
MCG
Off
Standby
Off
Optionally On¹
Off
Optionally On²
Off
Optionally On³
IIC
RTC
Off
Optionally on⁴
Standby
Optionally on⁴
SCI
Off
Standby
SPI
Off
Standby
TPM
Off
Standby
System Voltage Regulator
XOSC
Off
Standby
Off
Optionally On⁵
I/O Pins
USB (SIE and Transceiver)
States Held
Off
States Held
Optionally On⁶
USB 3.3-V Regulator
Off
Standby
USB RAM
Standby
Standby
1 _{Requires the asynchronous ADC clock and LVD to be enabled, else in standby.}
2 _{If ACGBS in ACMPSC is set, LVD must be enabled, else in standby.}
3 _{IRCLKEN and IREFSTEN set in MCGC1, else in standby.}
4 _{RTCPS[3:0] in RTCSC does not equal 0 before entering stop, else off.}
5 _{ERCLKEN and EREFSTEN set in MCGC2, else in standby. For high frequency range}
(RANGE in MCGC2 set) requires the LVD to also be enabled in stop3.
6 _{USBEN in CTL is set and USBPHYEN in USBCTL0 is set, else off.}
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor
39