33781 Datasheet, PDF (9/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75V ≤ V_CC ≤ 5.25V, 9.0V ≤ V_SUPn ≤ 25V,-40°C ≤ T_A ≤ 90°C, unless otherwise
noted. Voltages relative to GND, unless otherwise noted. Typical values noted reflect the approximate mean values of the
parameter at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CLOCK
CLK Periods (System requirement)⁽¹⁰⁾
Time High
Time Low
Period
CLK Transition (System requirement)⁽¹⁰⁾
Time for Low-to-High Transition of the CLK Input Signal
Time for High-to-Low Transition of the CLK Input Signal
Reset Low Time
SPI INTERFACE TIMING
t_CLKHI
t_CLKLO
t_CLKPER
t_CLKLH
t_CLKHL
t_RSTLO
ns
75
–
–
75
–
–
245
250
255
ns
–
–
100
–
–
100
100
–
–
ns
SPI Clock Cycle Time
SPI Clock High Time
SPI Clock Low Time
SPI CSn Lead Time⁽¹¹⁾
SPI CSn Lag Time⁽¹¹⁾
SPI CS0 Time Between Bursts⁽¹⁰⁾
SPI CS1 Time Between Bursts⁽¹⁰⁾
Data Setup Time
MOSI0 Valid Before SCLK0 Rising Edge⁽¹¹⁾
t_CYC
t_HI
t_LO
t_LEAD
t_LAG
t_CS0HI
t_CS1HI
t_SU
100
–
40
–
40
–
50
–
50
–
80
–
300
–
10
–
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
ns
–
Data Hold Time
MOSI0 Valid After SCLK0 Rising Edge^(11),(10)
t_H
Data Valid Time
t_V
SCLKn Falling Edge to MISOn Valid, C = 50pF⁽¹²⁾
ns
10
–
–
ns
–
–
25
Output Disable Time
CSn Rise to MISOn Hi-Z
Rise Time (30% V_CC to 70% V_CC)⁽¹⁰⁾
SCLKn, MOSI0
Fall Time (70% V_CC to 30% V_CC)⁽¹⁰⁾
SCLKn, MOSI0
t_DIS
ns
–
–
50
t_R
ns
–
–
10
t_F
ns
–
–
10
Notes
10. Not measured in production.
11. SPI signal timing from the production test equipment is programmed to ensure compliance.
12. Conditions are verified indirectly during test.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
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