33781 Datasheet, PDF (19/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
the driver. The over-voltage input causes the driver
characteristics to be modified under over-voltage conditions.
This is described in more detail in the Load Dump Operation
section.
A special requirement of the differential bus is to maintain
a low common mode voltage. This is accomplished by
monitoring the common mode voltage and modifying the
driver slew rates. This is the function of the Common Mode
Correction block.
Current signals sent by the slave are detected on both the
high side and the low side of the bus using a differential
current sense architecture. Sense resistors between the
Signal driver and the DnH and DnL outputs detect the slave
device response current. Sensing the current on both bus
lines improves the fault diagnostics of the bus. Also included
is an adder circuit which is used to improve the reception of
sensor data in the presence of common mode noise. The
comparators in the blocks output a high or low value
depending on if the input is above or below the signal
threshold.
The Receiver High, Receiver Low, and Receiver Sum
outputs are sent to the device logic block which is shown in
Figure 23. The data is sampled at the falling edge of DSIS. In
the presence of faults or common mode noise it is possible
that all three receiver circuits will not produce the same bit
pattern. To check for this, each of the three receiver filter
outputs is passed to a CRC generation and checking block.
A logic block determines which (if any) of the receiver filter
blocks has produced the correct result, by comparing the
CRC results along with the bit-by-bit XOR of the high side and
low side bit pattern. Table 7 shows how the logic determines
which (if any) receiver outputs contain a valid response. The
data is selected from either the Receiver High, Receiver Low
or Receiver Sum circuit and the ER bit is set accordingly in
the DnRnSTAT register.
If either Receiver High or Receiver Low has all 1’s for data,
including the CRC bits, then the ER bit will be set. For either
of these two conditions, the ER bit will be set regardless of
the Receiver Sum data value and regardless of whether or
not all the 1’s caused a CRC error on the High or Low side.
Note that SPI0 and SPI1 do not use the same sources for
their respective output data streams. SPI0 chooses between
Receiver High or Receiver Sum0; SPI1 chooses between
Receiver Low and Receiver Sum1.
In order to provide the maximum protection against a
single-point failure causing a disruption in communication,
the decision paths for the two SPI channels are internally
independent . For example, Receiver Sum0 and Receiver
Sum1 use different holding registers in the Receiver logic.
These registers are duplicates, although they will always hold
the same data unless there is a fault in one of the data paths.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
19