33781 Datasheet, PDF(16/44 Page) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

33781 Datasheet, PDF (16/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

◁

FUNCTIONAL DESCRIPTIONS

FUNCTIONAL PIN DESCRIPTIONS

LOW SIDE BUS (DnL)

There are four independent low side outputs, D0L, D1L,

D2L and D3L. They comprise the low side differential output

signal of the DBUS physical layer as shown in Figure 5. They

also provide power to the slave modules during the DBUS

idle time. The output of DnL should have a bypass capacitor

of 2.2nF to ground.

HIGH SIDE BUS (DnH)

There are four independent high side outputs, D0H, D1H,

D2H, and D3H. They comprise the high side differential

output signal of the DBUS physical layer. They also provide

power to the slave modules during the DBUS idle time. See

Figure 5. The output of DnH should have a bypass capacitor

of 2.2nF to ground.

POSITIVE SUPPLY FOR BUS OUTPUT (VSUPn)

This 9.0V to 25V power supply is used to provide power to

the slave devices attached to the DBUS. During the bus idle

time, the storage capacitors in the slave modules are charged

up to maintain a regulated supply to the slave device. VSUP1

powers devices DBUS0 and DBUS1, and VSUP2 powers

devices on DBUS2 and DBUS3. See Figure 9.

The two supplies are interdependent internally, however,

as can be seen in Figure 9: VSUP1 is used to create the

VCM_REF voltage for all four driver buffers, and VSUP2 is used

to supply the charge pump voltage. Consequently, both

VSUP1 and VSUP2 are required for internal functions: for

example, the internal voltage regulator VREG_8V is supplied

from VSUP1, but uses the VSUP2-derived charge pump

voltage to supply the output NMOS devices.

PSEUDO BUS (DPH AND DPL)

These bus high and bus low pins are created by closing

the pseudo bus switches attached to the D0H and D0L bus

lines internal to the 33781. This allows a second external set

of bus lines to communicate over the D0 Channel. The

pseudo bus switches are controlled by the system MCU

through SPI0.

VSUP1 (27)

GND (32)

RNE control for ch0, ch1, ch2

and ch3 status register

VSUP

Voltage

Monitor

VCP

VREG_8V

Voltage Regulator

V_8V

VMID

Reference

for common mode voltage

VCM_REF

DBUS 0

Driver/ Receiver

DBUS 1

DBUS 2

DBUS 3

Driver/ Receiver

VCP

VCharge_pump

D0H/L

D1H/L

GND (24)

D2H/L

D3H/L

VSUP2 (21)

Figure 9. VSUP Block Diagram

GND (18)

33781

Analog Integrated Circuit Device Data

Freescale Semiconductor

▷