33781 Datasheet, PDF (38/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES
OVER-CURRENT PROTECTION
Current limiters on the outputs prevent damage in the case
of shorts. Running in current limit results in high power
dissipation of the IC. If the power dissipation becomes high
enough, the die temperature will rise above its maximum
rating and an over-temperature circuit on the IC will shut
down the DBUS Driver/Receiver block.
Each channel high and low side bus drivers have current
limits for protection of both this device and slave devices
connected on the DBUS. During idle mode, the DnH drivers
have a high value current limit when sourcing current to allow
the drivers to charge the slave power storage capacitors, and
a lower value current limit when sinking current and slewing
the load capacitance. Conversely, the DnL drivers have a
high value current limit when they are sinking current, and a
lower value current limit when they are sourcing current.
In addition, the device monitors the current limit on each
channel to see if the channel is in “double current limit” during
every idle state. See ICL - Idle Mode Double Current Limit Bit
(Idle Mode Shutdown) on page 33. If the idle current limit is
detected, the ICL bit is set in the DnSTAT register for the next
DBUS transaction.
During signaling mode, the drivers incorporate a gross
current limit and an over-current shutdown. The current
shutdown is set at a low value, such that the channel high and
low side bus driver will shut down if the sourcing or sinking
current remains at a value larger than the response current.
The over-current shutdown is delayed by a filter to allow the
load capacitors to be slewed without causing a shutdown.
The purpose of the gross current limit is to protect the
drivers during the filter delay time. This current limit is set
higher than the peak current required to slew the load
capacitance.
The signals from the sourcing and sinking current
detection circuits are connected to a logical OR. The
combined signal passes through a common filter before
setting the over-current latch. During signaling mode, the
over-current shutdown disables both bus drivers and sets the
SDS (Signal Driver Shutdown) bit in the appropriate DnSTAT
register. The drivers remain high-impedance until the end of
Frame, when the bus returns to the Idle state.
The end of Frame clears the over-current shutdown state,
allowing the bus drivers to retry in the next Frame. However,
if the signal mode over-current shutdown occurs in two
sequential frames for the channel, the bus drivers are
disabled and can only be re-enabled on command from the
MCU. The ISDD bit is also set in the channel DEN register. If
the affected channel is channel 0 this set of conditions also
disables the pseudo bus switch.
THERMAL PROTECTION
Independent thermal protection is provided for each
channel and the Pseudo bus switches. The thermal limit cell
is located adjacent to the bus drivers for each channel, such
that both drivers are protected. When a thermal fault is
detected, the channel drivers are disabled (Hi-Z) until they
are re-enabled via the SPI. The thermal protection
incorporates hysteresis, preventing the channel bus drivers
from being re-enabled until the temperature has decreased.
Thermal fault information is reported via the DEN register.
See DnEN Register section for a description of the fault
reporting and clearing of the EN bits.
LOAD DUMP OPERATION
During an over-voltage condition (e.g., when load dump is
applied at the VSUPn pins), the DBUS voltage waveform is
modified to ensure that power dissipation is minimized,
DBUS timing is not violated, and internal components are
protected.
The midpoint of the signalling voltage is clamped at about
13V, such that for V_SUPn greater than 26V, the signalling
voltage levels do not increase. An over-voltage detection
circuit connected to DnH, having a threshold at about 26V,
causes the slew rates and driver conditions to be modified.
For a Signal-to-Idle transition, this causes the DnH voltage to
rise rapidly to the Idle state, and the DnL voltage is
maintained close to zero. For an Idle-to-Signal transition, the
DnH voltage will decrease rapidly until the over-voltage
threshold is reached, when normal operation resumes.
During this rapid fall of DnH, the DnL voltage is maintained
close to zero by forcing that driver on. See Figure 6.
RESET FUNCTION
A low level on RST forces all internal registers to a known
(reset) state and the receive and transmit queue pointers are
reset. Because the DBUS channels are now disabled (ENn =
0), the DBUS lines are tri-stated.
ABORT FUNCTION
An abort is generated on a channel whenever a control
register (DnCTRL, DnPOLY, DnSEED, DnLENGTH,
DnSSCTRL or DnFSEL) is addressed while writing, even if
the data is unchanged. No other register writes cause an
abort, and reads of any register do not cause an abort. The
abort is only taken for the channel where the write occurs - all
other channels are not effected. The DEN register is not
affected by an abort.
The abort occurs as soon as the address of the control
register is received on the SPI. Any DBUS transfer that was
in progress is stopped, and DBUS lines return to their Idle
states. The abort condition remains true throughout the SPI0
write to the DBUS control registers. After the last bit of the
DBUS control register is written, the channel addressed
buffer data bits and the SPI1 registers are cleared, the status
register bits are reset, and the transmit and receive queue
pointers are reset for both SPI0 and SPI1. The programmed
inter-frame delay is then enforced (using the new values of
the delay control bits) to allow reservoir capacitors in remote
33781
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Analog Integrated Circuit Device Data
Freescale Semiconductor