33781 Datasheet, PDF (3/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

PIN CONNECTIONS
PIN CONNECTIONS
RST
1
SCLK0
2
MOSI0
3
MISO0
4
SCLK1
5
MISO1
6
CS0
7
AGND
8
CS1
9
VSS
10
VDD
11
VPP
12
VCC
13
CLK
14
TESTIN
15
TESTOUT
16
32
GND
31
DPL
30
D0L
29
DPH
28
D0H
27
VSUP1
26
D1H
25
D1L
24
GND
23
D2L
22
D2H
21
VSUP2
20
D3H
19
D3L
18
GND
17
VSS_IDDQ
Figure 3. 33781 Pin Connections
Table 1. 33781 Pin Definitions
A functional description of each Pin can be found in the Functional Pin Descriptions section beginning on page 15.
Pin
Pin Name Pin Function Formal Name
Definition
1
RST
Reset
IC Reset
A low level on this pin returns all registers to a known state as indicated
in the sections entitled SPI0 Register and Bit Descriptions and SPI1
Communications.
2
SCLK0
Input
SPI0 Serial Data Clock Clocks data in from and out to SPI0. MISO0 data changes on the negative
transition of SCLK0. MOSI0 is sampled on the positive edge of SCLK0.
3
MOSI0
Input
SPI0 Master Out Slave ^{SPI data into SPI0. This data input is sampled on the positive edge of}
In
SCLK0
4
MISO0
Output
SPI0 Master In Slave ^{SPI0 data sent to the MCU by this device. This data output changes on}
Out
the negative edge of SCLK0. When CS0 is high, this Pin is high-
impedance.
5
SCLK1
Input
SPI1 Serial Data Clock ^{Clocks data out from SPI1. MISO1 data changes on the negative}
transition of SCLK1.
6
MISO1
Output
SPI1 Master In Slave SPI1 data sent to the MCU by this device. This data output changes on
Out
the negative edge of SCLK1. When CS1 is high, this Pin is high-
impedance.
7
CS0
Input
SPI0 Chip Select When this signal is high, SPI signals on SPI0 are ignored. Asserting this
pin low starts an SPI0 transaction. The SPI0 transaction is signaled as
completed when this signal returns high.
8
AGND
Ground
Analog Ground Ground for the analog circuits. This pin is not connected internally to the
other grounds on the chip. It should be connected to a quiet ground on
the board.
9
CS1
Input
SPI1 Chip Select When this signal is high, SPI signals on SPI1 are ignored. Asserting this
pin low starts an SPI1 transaction. The SPI1 transaction is signaled as
completed when this signal returns high.
10
VSS
Ground
Digital Ground
Digital ground connected internally to the other on-chip grounds. This
ground is connected to circuits that will consume current during IDDQ
testing.
11
VDD
Power
Digital Voltage
Output of the Internal 2.5V regulator for the digital circuits. No external
current draw is allowed from this pin.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
3