33781 Datasheet, PDF (25/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
.
SPI
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit
Bit
Bit Bit
Bit
Bit
Data Bit
10 11 12 13 14 15
Read DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 A0 A1 A2 A3 C0 C1
Only
Figure 19. SPI1 Bit Encoding
DO[0:9]- Data Bits
The received data bits from the bus channel transaction. If
the transaction had any CRC or SDS errors (See page 32
and page 33), then these bits are set to all zeros.
A[0:3] - Sensor Address Bits
The address of the slave that sent the data. This is a copy
of the address sent out during the previous bus transaction.
C[0:1] - Channel indicator Bits
The bits indicate which bus channel the data came from.
“01” indicates channel 2, and “10” indicates channel 3.
DBUS COMMUNICATIONS
The DBUS messages contain data from the DnH and DnL
registers. A CRC pattern is automatically appended to each
message. The data and CRC lengths are programmed by the
DnLENGTH register. Figure 20 shows the structure of the
DBUS message.
Bit n
…………………
Bit 0
CRC n
……
CRC 0
Figure 20. DBUS Communications Message
DBUS Driver/Receiver communications involve a frame
(DSIF), a data signal (DSIS), and a data return (DSIR) signal.
These are signals internal to the IC associated with the
protocol engine.
A message starts with a falling edge on the DSIF signal,
which marks the start of a frame. There is a one bit-time delay
before the MSB of data appears on DSIS. Data bits start with
a falling edge on DSIS. The low time is 1/3 of the bit time for
a 1, and 2/3 of a bit time for a 0. Data is transmitted on DSIS
and received on DSIR simultaneously. Receive data is the
captured level on DSIR at the end of each bit time. As a
message is received, it is stored bit-by-bit into the appropriate
receive register. For each data value received, there is a one-
bit status flag (ER) to indicate whether or not there was a
CRC error while receiving the data. At the end of the bit time
for the last CRC bit, DSIF returns to a logic high (Idle level).
A minimum delay is imposed between successive frames as
determined by the DnCTRL register.
Users initiate a message by writing (via the SPI0 interface
from the MCU) to the high and low byte of the data registers
(DnRnH/L). Transactions are scheduled once the CS0 for
that transfer rises. When 9- to 16-bit messages are to be
sent, the user writes to the DnH register first, and then the
DnL register, before the combined 9 to 16-bit data value
DnH:DnL is sent on the DBUS. The user should first check
the TE status flag to be sure the command register is not full
before writing a new data value to DnH and/or DnL. When the
minimum inter-frame delay has been satisfied, and CS0 has
risen, and if no SPI0 framing error has occurred, DSIF will go
low, indicating the start of a new transfer frame.
At the end of a DBUS transfer (and after the CRC error
status is stable), the RNE flag is set to indicate there is data
in the register available to be read.
DATA RATE
The base data rate is determined by the system clock
(CLK) and the values in the DnFSEL register. The CLK is
assumed to be 4MHz. The CLK is converted to a 64MHz
internal clock with a digital PLL, which is used to form the bit
rate clock. The minimum bit clock period which may be
programmed is:
(1/16*f_CLK) x 320 = 5 usec
However, this period may not meet overall system
requirements for minimum bit time. Longer base clock
periods can be selected by using the DxFSEL register. There
are 8 bits in the DxFSEL register representing values from 0
to 255. The complete equation for determining the base clock
period is:
((1/16*f_CLK) x (320 +2x)) where x = 0 to 255
Table 8 gives some examples of the base data rate for
f_CLK = 4.0MHz.
Table 8. Examples of Base Data Rate
FSEL
Base Bit Period
(usec)
Base Bit Frequency
(kbps)
00000000
00000001
00001101
00101000
5.000
5.031
5.406
6.250
200.0
198.8
184.9
160.0
11111110
12.938
77.3
11111111
12.969
77.1
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
25