33781 Datasheet, PDF (21/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Spectrum block does this by multiplying the 8-bit value in the
DxFSEL register by 2 and then adding it to the number 320
(decimal). The user must choose a minimum bit time
appropriate for his system. Factors which must be considered
are the slave response time, bus wire delays, and the
minimum idle time needed to recharge the slave H_CAPs for
the channel.
To spread the spectrum beyond this minimum bit time a
random delay based on a multiple of 1/64 MHz periods can
be added to each bit. This delay is created by a Pseudo
Random Bit Sequence Generator from which a 7-bit random
number is created. This number is further qualified by the
maximum number of counts (chosen by the DEV[2:0] bits in
the DxSSCTL registers) allowed beyond the base time
period. The resulting value is added to the minimum bit time
and fed to the bit clock logic, which generates the DSI bit
clock.
It is important for the user to select a maximum deviation
value that is appropriate for the system. A larger maximum
deviation results in spreading the bit energy to more
frequencies. However, this number also establishes the
maximum period for any random bit on that channel. If the
system requires that a minimum number of bits be transferred
within a fixed time period, then the user must select a
minimum base bit time and maximum deviation time that will
meet the criteria.
4MHz Clock
PLL
Divide by 8
64MHz Clock
24-bit PRBS
7-bit random number
7
Deviation
Select
7
Maximum Count Deviation
(from DxSSCTL)
3
10
320
Base Time Period
(from DxFSEL)
Adder
8 ^{Mult x 2} 9
Adder
10
Figure 12. Spread Spectrum Block Diagram
Bit
Clock
Logic
Bit
Clock
Analog Integrated Circuit Device Data
Freescale Semiconductor
33781
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