33781 Datasheet, PDF (26/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CRC GENERATION /CHECKING
Whenever a message is sent on the DBUS, a 0- to 8-bit
CRC value is computed and serially sent as the next n bits
after the LSB of the data. The CRC length, polynomial, and
initial seed are determined by the CRCLEN[3:0],
CRCPOLY[7:0], and CRCSEED[7:0] control register fields.
The message, including the CRC bits, is passed along to a
remote peripheral, which computes a separate CRC value as
the message data is received. If this computed and CRC
does not agree with the CRC value received in the message,
the peripheral device considers the message invalid.
Messages received include a 0- to 8-bit CRC value, which
was computed in the peripheral device that is responding. As
the message is received, a separate 0- to 8-bit CRC value is
computed and is compared with the CRC value in the
received message. If these values do not agree, the message
is considered invalid and the ER status bit in the associate
DnRnSTAT register is set at the end of the message along
with the RNE bit.
When no remote peripheral responds to a message, the
data pattern received will be all zeros with a CRC value of 0,
which may be detected as a CRC error depending on the
values of CRCLEN[3:0], CRCPOLY[7:0], and
CRCSEED[7:0].
CRC COMPUTATION
The CRC algorithm uses a programmable initialization
value, or seed of CRCSEED[7:0], and a programmable
polynomial of CRCPOLY[7:0]. Figure 21 is a VHDL
description of the CRC algorithm for the DBUS standard 4-bit
CRC, with its initial value of 1010. A seed value is chosen so
that a zero data value will generate a CRC value of 1010. A
block diagram of the default CRC calculation is shown in
Figure 22.
--------------------------------------------------------------------------
-- Calculates the 4-bit CRC (x^4 + 1) serially for 8 to 16 bits of data.
--------------------------------------------------------------------------
constant CRCPoly: std_logic_vector: = “0001”; -- x^4 +1
constant InitCrc: std_logic_vector: = “1010”;
procedure SerialCalculateCRC4(CRC: input std_logic_vector;Data: in std_logic) is vari-
able Xor1: std_logic;
begin
Xor1: = CRC(3) xor Data;
CRC: = CRC(2 downto 0) & ‘0’; -- Shift left 1 bit
if Xor1 = ‘1’ then
CRC: = CRC xor CRCPoly
end if;
end SerialCalculateCRC4;
Figure 21. CRC Algorithm
C3
C2
C1
C0
T
T
T
T
Input Data
1X4 + 0X3 + 0X2 + 0X1 + +X0 = X4+1
Figure 22. Default CRC Block Diagram
MESSAGE SIZE SPECIAL CASES
The response to any 8- to 15-bit message is expected to
be another 8- to 15-bit message, and the response to any
16-bit message is expected to be another 16-bit message.
This gives rise to some special cases when there is a
transition from one message size to a different message size.
Some messages must be long words (16 bits of data), and
others can be short words (8 to 15 bits of data).
The following are examples where the word is a standard
DSI formatted short word (8 bits of data and 4 bits of CRC).
Example 1: If the previous message was a short word and
the current message is a long word, the response message
(which is also a short word) finishes before the current
message frame, and the CRC bits look like data bits in the
long word format. Since the CRC validation of this short word
message response is not reliable, this short word response
should not be used.
Example 2: If the previous message was a long word and
the current message is a short word, the response message
(which is also a long word) cannot finish before the current
message frame. Bits three to zero of the data and the CRC
bits are lost. Data bits seven to four of the 16-bit response
33781
26
Analog Integrated Circuit Device Data
Freescale Semiconductor