33781 Datasheet, PDF (36/44 Pages) Freescale Semiconductor, Inc – Quad DSI 2.02 Master with Differential Drive and Frequency Spreading

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SWLEN[3:0]–Short Word Length in Bits
These bits specify the bit length of the short word
command that will be sent onto the specified DBUS channel.
The reset value for these bits is 1000 (8 bits), which is the
default DSI value. Allowed SWLEN[3:0] values range from
8 bits to 15 bits. If an attempt is made to write a value that is
less than 8 bits, a 1 is automatically written to SWLEN3,
thereby making the register value greater than or equal to 8
bits.
CRCLEN[3:0]–CRC Length in Bits
These bits specify the bit length of CRCs that are sent out
with commands and read back in. The length is valid for both
short and long word commands. The reset value for these
bits is 0100 (4 bits), which is the default DSI value. Allowed
CRCLEN[3:0] values range from 0 bits (no CRC) to 8 bits. If
an attempt is made to write a value that is greater than 8 bits,
the value 8 (1000) is automatically written into this register.
The CRCLEN[3:0] value overrides the CRCPOLY and
CRCSEED bit values that are beyond what the CRCLEN[3:0]
specifies.
DnSSCTRL REGISTERS
These registers control the operation of the spread
spectrum circuits.
A write to the register will abort any current activity on the
bus. Any bit changes will take place on the next DBUS
transaction following the conclusion of the SPI write to this
register. The bit assignments are shown in Figure 33.
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
-
-
-
-
-
DEV2
DEV1
DEV0
Reset
0
0
0
0
0
0
0
0
Figure 33. Dn Spread Spectrum Control Register Bit Assignment
DEV[2:0]–Spread Spectrum Frequency Deviation for
Channel n
These bits control the frequency deviation of the spread
spectrum signalling.
DEV[2:0] = 000 - No Deviation.
DEV[2:0] = 001 - 16 1/64 MHz periods Max Deviation
DEV[2:0] = 010 - 32 1/64 MHz periods Max Deviation
DEV[2:0] = 011 - 64 1/64 MHz periods Max Deviation
DEV[2:0] = 100 - 78 1/64 MHz periods Max Deviation
The deviation is the max number of 1/64MHz time periods
which are randomly added to the base time period to achieve
the spread spectrum effect. So for example, if you choose
DEV=011, the bit time will randomly vary from the base time
period to the base time period plus 1 μsec in 64 equal steps.
The mode with deviation disabled may be used to achieve
fine control of the bit rate without frequency spreading.
DnFSEL REGISTERS
These read/write registers control the spread spectrum
base time period. There are four of these registers, one for
each DBUS channel. The bit assignments are shown in
Figure 34.
A write to one of these registers will abort any current
activity on the bus. Any bit changes will take place on the next
DBUS transaction following the conclusion of the SPI write to
the register. Refer to the Spread Spectrum section for more
detail.
SPI Data Bit
Read/Write
Reset
Bit 7
6
5
4
3
2
1
FSEL7
FSEL6
FSEL5
FSEL4
FSEL3
FSEL2
FSEL1
0
0
1
0
1
0
0
Figure 34. Dn Frequency Selection Register Bit Assignments
0
FSEL0
0
DnFSEL[7:0] - Channel Frequency Selection Bits
These bits select the channel base time period. These bits
determine the minimum bit time (maximum bit frequency for
a channel. The equation for the minimum bit time is:
((1/16*f_CLK) x (320 +2x)) where x = 0 to 255 (decimal)
The hex value for x in the equation is represented by the
FSEL[7:0] bits
With a 4MHz clock and these bits set to zero the max bit
rate is 200kbps. Table 8 gives some examples of the max bit
rate and minimum bit time for f_CLK = 4.0MHz.
MASKID REGISTER
This read-only register contains seven mask ID bits for the
silicon. This ID can reflect the version, design change
number, or other encoded information. The purpose is for the
central module CPU to be able to know what version of silicon
33781
36
Analog Integrated Circuit Device Data
Freescale Semiconductor