MC9S12DG128MPVE Datasheet, PDF (89/128 Pages) Freescale Semiconductor, Inc – Device User Guide

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A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V_SS5 or V_DD5).
Table A-1 Absolute Maximum Ratings¹
Num
Rating
Symbol
Min
Max Unit
1 I/O, Regulator and Analog Supply Voltage
V_DD5
-0.3
6.0
V
2 _{Digital Logic Supply Voltage} ²
V_DD
-0.3
3.0
V
3 _{PLL Supply Voltage} ²
V_DDPLL
-0.3
3.0
V
4 Voltage difference VDDX to VDDR and VDDA
5 Voltage difference VSSX to VSSR and VSSA
∆_VDDX
-0.3
∆_VSSX
-0.3
0.3
V
0.3
V
6 Digital I/O Input Voltage
V_IN
-0.3
6.0
V
7 Analog Reference
8 XFC, EXTAL, XTAL inputs
V_RH, V_RL
-0.3
V_ILV
-0.3
6.0
V
3.0
V
9 TEST input
V_TEST
-0.3
10.0
V
Instantaneous Maximum Current
10 _{Single pin limit for all digital I/O pins 3}
I_D
-25
+25
mA
Instantaneous Maximum Current
11 _{Single pin limit for XFC, EXTAL, XTAL4}
I_DL
-25
+25
mA
Instantaneous Maximum Current
12 _{Single pin limit for TEST 5}
I_DT
-0.25
0
mA
13 Storage Temperature Range
T
stg
– 65
155
°C
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V_SSX and V_DDX, V_SSR and V_DDR or V_SSA and V_DDA.
4. Those pins are internally clamped to V_SSPLL and V_DDPLL.
5. This pin is clamped low to V_SSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
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