MC9S12DG128MPVE Datasheet, PDF (2/128 Pages) Freescale Semiconductor, Inc – Device User Guide

MC9S12DT128B Device User G^Fu^rid^ee^e—^sV^c0^a1.^l0^e9 ^{Semiconductor, Inc.}
Revision History
Version Revision Effective
Number Date
Date
V01.00
18 Jun 18 June
2001
2001
V01.01
23 July
2001
23 July
2001
V01.02
23 Sep
2001
23 Sep
2001
V01.03
12 Oct
2001
12 Oct
2001
V01.04
27 Feb
2002
27 Feb
2002
V01.05
4 Mar
2002
4 Mar
2002
V01.06
8 July
2002
22 July
2002
V01.07
V01.08
16 Aug
2002
12 Sep
2002
16 Aug
2002
12 Sep
2002
V01.09
31 Oct
2002
31 Oct
2002
Author
Description of Changes
Initial version (parent doc v2.03 dug for dp256).
Updated version after review
Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections
Replaced Star12 by HCS12
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos
Increased VDD to 2.35V, removed min. oscillator startup
Removed Document order number except from Cover Sheet
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
Minor corrections in table 1-1 & section 1.5.1
Corrected register address mismatches in section 1.5.1
Removed document order no. from Revision History page
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing CAN1,
BDLC, IIC and/or Byteflight
Added oscillator clock connection to BDM in S12_CORE in fig 3-1
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations.
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
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