MC9S12DG128MPVE Datasheet, PDF (57/128 Pages) Freescale Semiconductor, Inc – Device User Guide

Freescale Semicond_Mu_C9c_St₁o_2Dr_T,₁I₂n_8Bc_D._{evice User Guide — V01.09}
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC
MCU
R
C_S
VDDPLL
C_P
VDDPLL
Figure 2-3 PLL Loop Filter Connections
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.
For More Information On This Product,
Go to: www.freescale.com