MC9S12DG128MPVE Datasheet, PDF (121/128 Pages) Freescale Semiconductor, Inc – Device User Guide

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Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, C_LOAD = 50pF
Num C
Rating
Symbol Min
1 P Frequency of operation (E-clock)
f_o
0
2 P Cycle time
t_cyc
40
3 D Pulse width, E low
PW_EL
19
4 D _{Pulse width, E high}¹
PW_EH
19
5 D Address delay time
t_AD
6 D Address valid time to E rise (PW_EL–t_AD)
t_AV
11
7 D Muxed address hold time
t_MAH
2
8 D Address hold to data valid
t_AHDS
7
9 D Data hold to address
t_DHA
2
10 D Read data setup time
t_DSR
13
11 D Read data hold time
t_DHR
0
12 D Write data delay time
t_DDW
13 D Write data hold time
t_DHW
2
14 D Write data setup time⁽¹⁾ (PW_EH–t_DDW)
t_DSW
12
15 D Address access time⁽¹⁾ (t_cyc–t_AD–t_DSR)
t_ACCA
19
16 D E high access time⁽¹⁾ (PW_EH–t_DSR)
t_ACCE
6
17 D Non-multiplexed address delay time
t_NAD
18 D Non-muxed address valid to E rise (PW_EL–t_NAD)
t_NAV
15
19 D Non-multiplexed address hold time
t_NAH
2
20 D Chip select delay time
t_CSD
21 D Chip select access time⁽¹⁾ (t_cyc–t_CSD–t_DSR)
t_ACCS
11
22 D Chip select hold time
t_CSH
2
23 D Chip select negated time
t_CSN
8
24 D Read/write delay time
t_RWD
25 D Read/write valid time to E rise (PW_EL–t_RWD)
t_RWV
14
26 D Read/write hold time
t_RWH
2
27 D Low strobe delay time
t_LSD
28 D Low strobe valid time to E rise (PW_EL–t_LSD)
t_LSV
14
29 D Low strobe hold time
t_LSH
2
30 D NOACC strobe delay time
t_NOD
31 D NOACC valid time to E rise (PW_EL–t_NOD)
t_NOV
14
Typ
Max
25.0
8
7
6
16
7
7
7
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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