MC9S12DG128MPVE Datasheet, PDF (115/128 Pages) Freescale Semiconductor, Inc – Device User Guide

A.7 SPI
Freescale Semicond_Mu_C9c_St₁o_2Dr_T,₁I₂n_8Bc_D._{evice User Guide — V01.09}
A.7.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-18.
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
2
1
4
4
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
5
6
MSB IN²
BIT 6 . . . 1
MOSI
(OUTPUT)
9
MSB OUT²
9
BIT 6 . . . 1
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
11
3
12
LSB IN
10
LSB OUT
Figure A-5 SPI Master Timing (CPHA = 0)
For More Information On This Product,
Go to: www.freescale.com